1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices by performing a novel deposition-etch-deposition process flow.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. One technique used to form STI structures initially involves growing a pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layer are patterned. Then, an etching process is performed to form a trench in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process, such as the well-known High Aspect Ratio Process (HARP) offered by Applied Materials, is performed to overfill the trenches with an insulating material such as silicon dioxide. The deposited silicon dioxide material in the process is then typically densified by subjecting it to an anneal process in a furnace, e.g., about 1000° C. for a duration of about 30 minutes. The purpose of the densification process is to increase the etch resistance of the silicon dioxide material to later wet etching processes. Thereafter, a chemical mechanical polishing (CMP) process is then performed using the pad nitride layer as a polish stop layer to remove the excess insulation material positioned outside of the trenches. Then, a subsequent deglazing (etching) process may be performed to insure that the silicon dioxide insulating material is removed from the surface of the pad nitride layer. This deglaze process may remove some of material of the STI structures. Thereafter, a wet nitride strip process, e.g., a hot phosphoric acid process, is performed to selectively remove the pad nitride layer relative to the pad oxide layer and the STI structure. If desired, the pad oxide layer may also be removed at this time by performing a quick wet etching process using a dilute HF chemistry. Alternatively, the pad oxide layer may be left in place or removed at a later point in the process flow.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. The attacks are not uniform across the surface of the STI structure due to, for example, masking only certain portions of the STI structure during some etching processes. As a result, there is an uneven loss of material in the STI structure, sometimes referred to as “divots.”
FIG. 1 is a scanning electron microscope image of an illustrative prior art STI structure 11. The STI structure 11 is formed in a substrate 13 by performing the processing generally described above, i.e., the trench is formed in the substrate 13 and thereafter filled with an insulating material by performing a single HARP deposition process. At the point depicted in FIG. 1, an illustrative gate structure has been formed above the substrate 13 and the STI structure 11. The view in FIG. 1 is a cross-sectional view of the gate structure taken along a direction that would correspond to the gate width direction of a transistor device. As depicted therein, various layers of material that make up the gate structure have been formed across the substrate 11: a gate insulation layer 15 (e.g., silicon dioxide), a high-k layer of insulating material 17 (a material having a k value greater than 10), a metal layer 19 (e.g., titanium nitride) and a layer of polysilicon 21. The upper surface of the STI structure 11 has a plurality of divots 11A, 11B located adjacent the substrate 13 and a relatively flat central section 11F located between the two divots 11A, 11B. In this example, relative to the upper surface of the substrate 13, the divots 11A, 11B may have a depth of about 6.9 nm and 7.5 nm, respectively. The relatively flat surface 11F may be positioned about 6 nm above the surface of the substrate 13.
Divots, such as the illustrative divots 11A, 11B depicted in FIG. 1, can be problematic for several reasons. If the depth of the divots are too great, the chances that there may be a loss of gate encapsulation as processing continues may occur. The presence of such divots may cause an increase in the degree of undesirable “footing” of the gate materials when they are patterned to define the gate structure. In some cases, the depth of the divots may be so great that there is a risk of incomplete etching for one or more of the conductive materials in the gate structure such that there is a short-circuit created between adjacent gate structures. Such a situation is sometimes referred to as the creation of undesirable “poly stringers” between adjacent gate structures. As a result, the STI structures may not perform their isolation function as intended, which may result in problems such as increased leakage currents, device failure, etc.
The present disclosure is directed to various methods of forming isolation structures that may eliminate or at least reduce one or more of the problems identified above.